mmx.h

00001 /*
00002     mmx.h
00003 
00004     MultiMedia eXtensions GCC interface library for IA32.
00005 
00006     To use this library, simply include this header file
00007     and compile with GCC.  You MUST have inlining enabled
00008     in order for mmx_ok() to work; this can be done by
00009     simply using -O on the GCC command line.
00010 
00011     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
00012     EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
00013     LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
00014     AND FITNESS FOR ANY PARTICULAR PURPOSE.
00015 
00016     1997-98 by H. Dietz and R. Fisher
00017 
00018     $Id: mmx.h,v 1.3 2005/12/06 14:34:03 steveu Exp $
00019 */
00020 
00021 #if !defined(_SPANDSP_MMX_H_)
00022 #define _SPANDSP_MMX_H_
00023 
00024 #if defined(__i386__)
00025 /*
00026     The type of an value that fits in an MMX register
00027     (note that long long constant values MUST be suffixed
00028     by LL and unsigned long long values by ULL, lest
00029     they be truncated by the compiler)
00030 */
00031 typedef union
00032 {
00033     int64_t     q;      /* Quadword (64-bit) value */
00034     uint64_t    uq;     /* Unsigned Quadword */
00035     int32_t     d[2];   /* 2 Doubleword (32-bit) values */
00036     uint32_t    ud[2];  /* 2 Unsigned Doubleword */
00037     int16_t     w[4];   /* 4 Word (16-bit) values */
00038     uint16_t    uw[4];  /* 4 Unsigned Word */
00039     int8_t      b[8];   /* 8 Byte (8-bit) values */
00040     uint8_t     ub[8];  /* 8 Unsigned Byte */
00041     float       s[2];   /* Single-precision (32-bit) value */
00042 } mmx_t;
00043 
00044 typedef union
00045 {
00046     int64_t     q[2];   /* Quadword (64-bit) value */
00047     uint64_t    uq[2];  /* Unsigned Quadword */
00048     int32_t     d[4];   /* 2 Doubleword (32-bit) values */
00049     uint32_t    ud[4];  /* 2 Unsigned Doubleword */
00050     int16_t     w[8];   /* 4 Word (16-bit) values */
00051     uint16_t    uw[8];  /* 4 Unsigned Word */
00052     int8_t      b[16];  /* 8 Byte (8-bit) values */
00053     uint8_t     ub[16]; /* 8 Unsigned Byte */
00054     float       s[4];   /* Single-precision (32-bit) value */
00055 } xmm_t;
00056 
00057 #if defined(__cplusplus)
00058 extern "C"
00059 {
00060 #endif
00061 
00062 /*
00063     Function to test if multimedia instructions are supported...
00064 */
00065 static inline int mm_support(void)
00066 {
00067     /* Returns 1 if MMX instructions are supported,
00068        3 if Cyrix MMX and Extended MMX instructions are supported
00069        5 if AMD MMX and 3DNow! instructions are supported
00070        0 if hardware does not support any of these
00071     */
00072     register int rval = 0;
00073 
00074     __asm__ __volatile__ (
00075         /* See if CPUID instruction is supported ... */
00076         /* ... Get copies of EFLAGS into eax and ecx */
00077         "pushf\n\t"
00078         "popl %%eax\n\t"
00079         "movl %%eax, %%ecx\n\t"
00080 
00081         /* ... Toggle the ID bit in one copy and store */
00082         /*     to the EFLAGS reg */
00083         "xorl $0x200000, %%eax\n\t"
00084         "push %%eax\n\t"
00085         "popf\n\t"
00086 
00087         /* ... Get the (hopefully modified) EFLAGS */
00088         "pushf\n\t"
00089         "popl %%eax\n\t"
00090 
00091         /* ... Compare and test result */
00092         "xorl %%eax, %%ecx\n\t"
00093         "testl $0x200000, %%ecx\n\t"
00094         "jz NotSupported1\n\t"              /* Nothing supported */
00095 
00096 
00097         /* Get standard CPUID information, and
00098            go to a specific vendor section */
00099         "movl $0, %%eax\n\t"
00100         "cpuid\n\t"
00101 
00102         /* Check for Intel */
00103         "cmpl $0x756e6547, %%ebx\n\t"
00104         "jne TryAMD\n\t"
00105         "cmpl $0x49656e69, %%edx\n\t"
00106         "jne TryAMD\n\t"
00107         "cmpl $0x6c65746e, %%ecx\n"
00108         "jne TryAMD\n\t"
00109         "jmp Intel\n\t"
00110 
00111         /* Check for AMD */
00112         "\nTryAMD:\n\t"
00113         "cmpl $0x68747541, %%ebx\n\t"
00114         "jne TryCyrix\n\t"
00115         "cmpl $0x69746e65, %%edx\n\t"
00116         "jne TryCyrix\n\t"
00117         "cmpl $0x444d4163, %%ecx\n"
00118         "jne TryCyrix\n\t"
00119         "jmp AMD\n\t"
00120 
00121         /* Check for Cyrix */
00122         "\nTryCyrix:\n\t"
00123         "cmpl $0x69727943, %%ebx\n\t"
00124         "jne NotSupported2\n\t"
00125         "cmpl $0x736e4978, %%edx\n\t"
00126         "jne NotSupported3\n\t"
00127         "cmpl $0x64616574, %%ecx\n\t"
00128         "jne NotSupported4\n\t"
00129         /* Drop through to Cyrix... */
00130 
00131 
00132         /* Cyrix Section */
00133         /* See if extended CPUID is supported */
00134         "movl $0x80000000, %%eax\n\t"
00135         "cpuid\n\t"
00136         "cmpl $0x80000000, %%eax\n\t"
00137         "jl MMXtest\n\t"                    /* Try standard CPUID instead */
00138 
00139         /* Extended CPUID supported, so get extended features */
00140         "movl $0x80000001, %%eax\n\t"
00141         "cpuid\n\t"
00142         "testl $0x00800000, %%eax\n\t"      /* Test for MMX */
00143         "jz NotSupported5\n\t"              /* MMX not supported */
00144         "testl $0x01000000, %%eax\n\t"      /* Test for Ext'd MMX */
00145         "jnz EMMXSupported\n\t"
00146         "movl $1, %0:\n\n\t"                /* MMX Supported */
00147         "jmp Return\n\n"
00148         "EMMXSupported:\n\t"
00149         "movl $3, %0:\n\n\t"                /* EMMX and MMX Supported */
00150         "jmp Return\n\t"
00151 
00152 
00153         /* AMD Section */
00154         "AMD:\n\t"
00155 
00156         /* See if extended CPUID is supported */
00157         "movl $0x80000000, %%eax\n\t"
00158         "cpuid\n\t"
00159         "cmpl $0x80000000, %%eax\n\t"
00160         "jl MMXtest\n\t"                    /* Try standard CPUID instead */
00161 
00162         /* Extended CPUID supported, so get extended features */
00163         "movl $0x80000001, %%eax\n\t"
00164         "cpuid\n\t"
00165         "testl $0x00800000, %%edx\n\t"      /* Test for MMX */
00166         "jz NotSupported6\n\t"              /* MMX not supported */
00167         "testl $0x80000000, %%edx\n\t"      /* Test for 3DNow! */
00168         "jnz ThreeDNowSupported\n\t"
00169         "movl $1, %0:\n\n\t"                /* MMX Supported */
00170         "jmp Return\n\n"
00171         "ThreeDNowSupported:\n\t"
00172         "movl $5, %0:\n\n\t"                /* 3DNow! and MMX Supported */
00173         "jmp Return\n\t"
00174 
00175 
00176         /* Intel Section */
00177         "Intel:\n\t"
00178 
00179         /* Check for MMX */
00180         "MMXtest:\n\t"
00181         "movl $1, %%eax\n\t"
00182         "cpuid\n\t"
00183         "testl $0x00800000, %%edx\n\t"      /* Test for MMX */
00184         "jz NotSupported7\n\t"              /* MMX Not supported */
00185         "movl $1, %0:\n\n\t"                /* MMX Supported */
00186         "jmp Return\n\t"
00187 
00188         /* Nothing supported */
00189         "\nNotSupported1:\n\t"
00190         "#movl $101, %0:\n\n\t"
00191         "\nNotSupported2:\n\t"
00192         "#movl $102, %0:\n\n\t"
00193         "\nNotSupported3:\n\t"
00194         "#movl $103, %0:\n\n\t"
00195         "\nNotSupported4:\n\t"
00196         "#movl $104, %0:\n\n\t"
00197         "\nNotSupported5:\n\t"
00198         "#movl $105, %0:\n\n\t"
00199         "\nNotSupported6:\n\t"
00200         "#movl $106, %0:\n\n\t"
00201         "\nNotSupported7:\n\t"
00202         "#movl $107, %0:\n\n\t"
00203         "movl $0, %0:\n\n\t"
00204 
00205         "Return:\n\t"
00206         : "=a" (rval)
00207         : /* no input */
00208         : "eax", "ebx", "ecx", "edx"
00209     );
00210 
00211     /* Return */
00212     return(rval);
00213 }
00214 
00215 /*
00216     Function to test if mmx instructions are supported...
00217 */
00218 static inline int mmx_ok(void)
00219 {
00220     /* Returns 1 if MMX instructions are supported, 0 otherwise */
00221     return (mm_support() & 0x1);
00222 }
00223 
00224 /*
00225     Helper functions for the instruction macros that follow...
00226     (note that memory-to-register, m2r, instructions are nearly
00227     as efficient as register-to-register, r2r, instructions;
00228     however, memory-to-memory instructions are really simulated
00229     as a convenience, and are only 1/3 as efficient)
00230 */
00231 #define mmx_i2r(op, imm, reg) \
00232     __asm__ __volatile__ (#op " $" #imm ", %%" #reg \
00233                           : /* nothing */ \
00234                           : /* nothing */);
00235 
00236 #define mmx_m2r(op, mem, reg) \
00237     __asm__ __volatile__ (#op " %0, %%" #reg \
00238                           : /* nothing */ \
00239                           : "X" (mem))
00240 
00241 #define mmx_r2m(op, reg, mem) \
00242     __asm__ __volatile__ (#op " %%" #reg ", %0" \
00243                           : "=X" (mem) \
00244                           : /* nothing */ )
00245 
00246 #define mmx_r2r(op, regs, regd) \
00247     __asm__ __volatile__ (#op " %" #regs ", %" #regd)
00248 
00249 #define mmx_m2m(op, mems, memd) \
00250     __asm__ __volatile__ ("movq %0, %%mm0\n\t" \
00251                           #op " %1, %%mm0\n\t" \
00252                           "movq %%mm0, %0" \
00253                           : "=X" (memd) \
00254                           : "X" (mems))
00255 
00256 /*
00257     1x64 MOVe Quadword
00258     (this is both a load and a store...
00259     in fact, it is the only way to store)
00260 */
00261 #define movq_m2r(var, reg)          mmx_m2r(movq, var, reg)
00262 #define movq_r2m(reg, var)          mmx_r2m(movq, reg, var)
00263 #define movq_r2r(regs, regd)        mmx_r2r(movq, regs, regd)
00264 #define movq(vars, vard) \
00265     __asm__ __volatile__ ("movq %1, %%mm0\n\t" \
00266                           "movq %%mm0, %0" \
00267                           : "=X" (vard) \
00268                           : "X" (vars))
00269 
00270 /*
00271     1x32 MOVe Doubleword
00272     (like movq, this is both load and store...
00273     but is most useful for moving things between
00274     mmx registers and ordinary registers)
00275 */
00276 #define movd_m2r(var, reg)          mmx_m2r(movd, var, reg)
00277 #define movd_r2m(reg, var)          mmx_r2m(movd, reg, var)
00278 #define movd_r2r(regs, regd)        mmx_r2r(movd, regs, regd)
00279 #define movd(vars, vard) \
00280     __asm__ __volatile__ ("movd %1, %%mm0\n\t" \
00281                           "movd %%mm0, %0" \
00282                           : "=X" (vard) \
00283                           : "X" (vars))
00284 
00285 /*
00286     2x32, 4x16, and 8x8 Parallel ADDs
00287 */
00288 #define paddd_m2r(var, reg)         mmx_m2r(paddd, var, reg)
00289 #define paddd_r2r(regs, regd)       mmx_r2r(paddd, regs, regd)
00290 #define paddd(vars, vard)           mmx_m2m(paddd, vars, vard)
00291 
00292 #define paddw_m2r(var, reg)         mmx_m2r(paddw, var, reg)
00293 #define paddw_r2r(regs, regd)       mmx_r2r(paddw, regs, regd)
00294 #define paddw(vars, vard)           mmx_m2m(paddw, vars, vard)
00295 
00296 #define paddb_m2r(var, reg)         mmx_m2r(paddb, var, reg)
00297 #define paddb_r2r(regs, regd)       mmx_r2r(paddb, regs, regd)
00298 #define paddb(vars, vard)           mmx_m2m(paddb, vars, vard)
00299 
00300 /*
00301     4x16 and 8x8 Parallel ADDs using Saturation arithmetic
00302 */
00303 #define paddsw_m2r(var, reg)        mmx_m2r(paddsw, var, reg)
00304 #define paddsw_r2r(regs, regd)      mmx_r2r(paddsw, regs, regd)
00305 #define paddsw(vars, vard)          mmx_m2m(paddsw, vars, vard)
00306 
00307 #define paddsb_m2r(var, reg)        mmx_m2r(paddsb, var, reg)
00308 #define paddsb_r2r(regs, regd)      mmx_r2r(paddsb, regs, regd)
00309 #define paddsb(vars, vard)          mmx_m2m(paddsb, vars, vard)
00310 
00311 /*
00312     4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
00313 */
00314 #define paddusw_m2r(var, reg)       mmx_m2r(paddusw, var, reg)
00315 #define paddusw_r2r(regs, regd)     mmx_r2r(paddusw, regs, regd)
00316 #define paddusw(vars, vard)         mmx_m2m(paddusw, vars, vard)
00317 
00318 #define paddusb_m2r(var, reg)       mmx_m2r(paddusb, var, reg)
00319 #define paddusb_r2r(regs, regd)     mmx_r2r(paddusb, regs, regd)
00320 #define paddusb(vars, vard)         mmx_m2m(paddusb, vars, vard)
00321 
00322 /*
00323     2x32, 4x16, and 8x8 Parallel SUBs
00324 */
00325 #define psubd_m2r(var, reg)         mmx_m2r(psubd, var, reg)
00326 #define psubd_r2r(regs, regd)       mmx_r2r(psubd, regs, regd)
00327 #define psubd(vars, vard)           mmx_m2m(psubd, vars, vard)
00328 
00329 #define psubw_m2r(var, reg)         mmx_m2r(psubw, var, reg)
00330 #define psubw_r2r(regs, regd)       mmx_r2r(psubw, regs, regd)
00331 #define psubw(vars, vard)           mmx_m2m(psubw, vars, vard)
00332 
00333 #define psubb_m2r(var, reg)         mmx_m2r(psubb, var, reg)
00334 #define psubb_r2r(regs, regd)       mmx_r2r(psubb, regs, regd)
00335 #define psubb(vars, vard)           mmx_m2m(psubb, vars, vard)
00336 
00337 /*
00338     4x16 and 8x8 Parallel SUBs using Saturation arithmetic
00339 */
00340 #define psubsw_m2r(var, reg)        mmx_m2r(psubsw, var, reg)
00341 #define psubsw_r2r(regs, regd)      mmx_r2r(psubsw, regs, regd)
00342 #define psubsw(vars, vard)          mmx_m2m(psubsw, vars, vard)
00343 
00344 #define psubsb_m2r(var, reg)        mmx_m2r(psubsb, var, reg)
00345 #define psubsb_r2r(regs, regd)      mmx_r2r(psubsb, regs, regd)
00346 #define psubsb(vars, vard)          mmx_m2m(psubsb, vars, vard)
00347 
00348 /*
00349     4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
00350 */
00351 #define psubusw_m2r(var, reg)       mmx_m2r(psubusw, var, reg)
00352 #define psubusw_r2r(regs, regd)     mmx_r2r(psubusw, regs, regd)
00353 #define psubusw(vars, vard)         mmx_m2m(psubusw, vars, vard)
00354 
00355 #define psubusb_m2r(var, reg)       mmx_m2r(psubusb, var, reg)
00356 #define psubusb_r2r(regs, regd)     mmx_r2r(psubusb, regs, regd)
00357 #define psubusb(vars, vard)         mmx_m2m(psubusb, vars, vard)
00358 
00359 /*
00360     4x16 Parallel MULs giving Low 4x16 portions of results
00361 */
00362 #define pmullw_m2r(var, reg)        mmx_m2r(pmullw, var, reg)
00363 #define pmullw_r2r(regs, regd)      mmx_r2r(pmullw, regs, regd)
00364 #define pmullw(vars, vard)          mmx_m2m(pmullw, vars, vard)
00365 
00366 /*
00367     4x16 Parallel MULs giving High 4x16 portions of results
00368 */
00369 #define pmulhw_m2r(var, reg)        mmx_m2r(pmulhw, var, reg)
00370 #define pmulhw_r2r(regs, regd)      mmx_r2r(pmulhw, regs, regd)
00371 #define pmulhw(vars, vard)          mmx_m2m(pmulhw, vars, vard)
00372 
00373 /*
00374     4x16->2x32 Parallel Mul-ADD
00375     (muls like pmullw, then adds adjacent 16-bit fields
00376     in the multiply result to make the final 2x32 result)
00377 */
00378 #define pmaddwd_m2r(var, reg)       mmx_m2r(pmaddwd, var, reg)
00379 #define pmaddwd_r2r(regs, regd)     mmx_r2r(pmaddwd, regs, regd)
00380 #define pmaddwd(vars, vard)         mmx_m2m(pmaddwd, vars, vard)
00381 
00382 /*
00383     1x64 bitwise AND
00384 */
00385 #define pand_m2r(var, reg)          mmx_m2r(pand, var, reg)
00386 #define pand_r2r(regs, regd)        mmx_r2r(pand, regs, regd)
00387 #define pand(vars, vard)            mmx_m2m(pand, vars, vard)
00388 
00389 /*
00390     1x64 bitwise AND with Not the destination
00391 */
00392 #define pandn_m2r(var, reg)         mmx_m2r(pandn, var, reg)
00393 #define pandn_r2r(regs, regd)       mmx_r2r(pandn, regs, regd)
00394 #define pandn(vars, vard)           mmx_m2m(pandn, vars, vard)
00395 
00396 /*
00397     1x64 bitwise OR
00398 */
00399 #define por_m2r(var, reg)           mmx_m2r(por, var, reg)
00400 #define por_r2r(regs, regd)         mmx_r2r(por, regs, regd)
00401 #define por(vars, vard)             mmx_m2m(por, vars, vard)
00402 
00403 /*
00404     1x64 bitwise eXclusive OR
00405 */
00406 #define pxor_m2r(var, reg)          mmx_m2r(pxor, var, reg)
00407 #define pxor_r2r(regs, regd)        mmx_r2r(pxor, regs, regd)
00408 #define pxor(vars, vard)            mmx_m2m(pxor, vars, vard)
00409 
00410 /*
00411     2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
00412     (resulting fields are either 0 or -1)
00413 */
00414 #define pcmpeqd_m2r(var, reg)       mmx_m2r(pcmpeqd, var, reg)
00415 #define pcmpeqd_r2r(regs, regd)     mmx_r2r(pcmpeqd, regs, regd)
00416 #define pcmpeqd(vars, vard)         mmx_m2m(pcmpeqd, vars, vard)
00417 
00418 #define pcmpeqw_m2r(var, reg)       mmx_m2r(pcmpeqw, var, reg)
00419 #define pcmpeqw_r2r(regs, regd)     mmx_r2r(pcmpeqw, regs, regd)
00420 #define pcmpeqw(vars, vard)         mmx_m2m(pcmpeqw, vars, vard)
00421 
00422 #define pcmpeqb_m2r(var, reg)       mmx_m2r(pcmpeqb, var, reg)
00423 #define pcmpeqb_r2r(regs, regd)     mmx_r2r(pcmpeqb, regs, regd)
00424 #define pcmpeqb(vars, vard)         mmx_m2m(pcmpeqb, vars, vard)
00425 
00426 /*
00427     2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
00428     (resulting fields are either 0 or -1)
00429 */
00430 #define pcmpgtd_m2r(var, reg)       mmx_m2r(pcmpgtd, var, reg)
00431 #define pcmpgtd_r2r(regs, regd)     mmx_r2r(pcmpgtd, regs, regd)
00432 #define pcmpgtd(vars, vard)         mmx_m2m(pcmpgtd, vars, vard)
00433 
00434 #define pcmpgtw_m2r(var, reg)       mmx_m2r(pcmpgtw, var, reg)
00435 #define pcmpgtw_r2r(regs, regd)     mmx_r2r(pcmpgtw, regs, regd)
00436 #define pcmpgtw(vars, vard)         mmx_m2m(pcmpgtw, vars, vard)
00437 
00438 #define pcmpgtb_m2r(var, reg)       mmx_m2r(pcmpgtb, var, reg)
00439 #define pcmpgtb_r2r(regs, regd)     mmx_r2r(pcmpgtb, regs, regd)
00440 #define pcmpgtb(vars, vard)         mmx_m2m(pcmpgtb, vars, vard)
00441 
00442 /*
00443     1x64, 2x32, and 4x16 Parallel Shift Left Logical
00444 */
00445 #define psllq_i2r(imm, reg)         mmx_i2r(psllq, imm, reg)
00446 #define psllq_m2r(var, reg)         mmx_m2r(psllq, var, reg)
00447 #define psllq_r2r(regs, regd)       mmx_r2r(psllq, regs, regd)
00448 #define psllq(vars, vard)           mmx_m2m(psllq, vars, vard)
00449 
00450 #define pslld_i2r(imm, reg)         mmx_i2r(pslld, imm, reg)
00451 #define pslld_m2r(var, reg)         mmx_m2r(pslld, var, reg)
00452 #define pslld_r2r(regs, regd)       mmx_r2r(pslld, regs, regd)
00453 #define pslld(vars, vard)           mmx_m2m(pslld, vars, vard)
00454 
00455 #define psllw_i2r(imm, reg)         mmx_i2r(psllw, imm, reg)
00456 #define psllw_m2r(var, reg)         mmx_m2r(psllw, var, reg)
00457 #define psllw_r2r(regs, regd)       mmx_r2r(psllw, regs, regd)
00458 #define psllw(vars, vard)           mmx_m2m(psllw, vars, vard)
00459 
00460 /*
00461     1x64, 2x32, and 4x16 Parallel Shift Right Logical
00462 */
00463 #define psrlq_i2r(imm, reg)         mmx_i2r(psrlq, imm, reg)
00464 #define psrlq_m2r(var, reg)         mmx_m2r(psrlq, var, reg)
00465 #define psrlq_r2r(regs, regd)       mmx_r2r(psrlq, regs, regd)
00466 #define psrlq(vars, vard)           mmx_m2m(psrlq, vars, vard)
00467 
00468 #define psrld_i2r(imm, reg)         mmx_i2r(psrld, imm, reg)
00469 #define psrld_m2r(var, reg)         mmx_m2r(psrld, var, reg)
00470 #define psrld_r2r(regs, regd)       mmx_r2r(psrld, regs, regd)
00471 #define psrld(vars, vard)           mmx_m2m(psrld, vars, vard)
00472 
00473 #define psrlw_i2r(imm, reg)         mmx_i2r(psrlw, imm, reg)
00474 #define psrlw_m2r(var, reg)         mmx_m2r(psrlw, var, reg)
00475 #define psrlw_r2r(regs, regd)       mmx_r2r(psrlw, regs, regd)
00476 #define psrlw(vars, vard)           mmx_m2m(psrlw, vars, vard)
00477 
00478 /*
00479     2x32 and 4x16 Parallel Shift Right Arithmetic
00480 */
00481 #define psrad_i2r(imm, reg)         mmx_i2r(psrad, imm, reg)
00482 #define psrad_m2r(var, reg)         mmx_m2r(psrad, var, reg)
00483 #define psrad_r2r(regs, regd)       mmx_r2r(psrad, regs, regd)
00484 #define psrad(vars, vard)           mmx_m2m(psrad, vars, vard)
00485 
00486 #define psraw_i2r(imm, reg)         mmx_i2r(psraw, imm, reg)
00487 #define psraw_m2r(var, reg)         mmx_m2r(psraw, var, reg)
00488 #define psraw_r2r(regs, regd)       mmx_r2r(psraw, regs, regd)
00489 #define psraw(vars, vard)           mmx_m2m(psraw, vars, vard)
00490 
00491 
00492 /*
00493     2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
00494     (packs source and dest fields into dest in that order)
00495 */
00496 #define packssdw_m2r(var, reg)      mmx_m2r(packssdw, var, reg)
00497 #define packssdw_r2r(regs, regd)    mmx_r2r(packssdw, regs, regd)
00498 #define packssdw(vars, vard)        mmx_m2m(packssdw, vars, vard)
00499 
00500 #define packsswb_m2r(var, reg)      mmx_m2r(packsswb, var, reg)
00501 #define packsswb_r2r(regs, regd)    mmx_r2r(packsswb, regs, regd)
00502 #define packsswb(vars, vard)        mmx_m2m(packsswb, vars, vard)
00503 
00504 
00505 /*
00506     4x16->8x8 PACK and Unsigned Saturate
00507     (packs source and dest fields into dest in that order)
00508 */
00509 #define packuswb_m2r(var, reg)      mmx_m2r(packuswb, var, reg)
00510 #define packuswb_r2r(regs, regd)    mmx_r2r(packuswb, regs, regd)
00511 #define packuswb(vars, vard)        mmx_m2m(packuswb, vars, vard)
00512 
00513 /*
00514     2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
00515     (interleaves low half of dest with low half of source
00516     as padding in each result field)
00517 */
00518 #define punpckldq_m2r(var, reg)     mmx_m2r(punpckldq, var, reg)
00519 #define punpckldq_r2r(regs, regd)   mmx_r2r(punpckldq, regs, regd)
00520 #define punpckldq(vars, vard)       mmx_m2m(punpckldq, vars, vard)
00521 
00522 #define punpcklwd_m2r(var, reg)     mmx_m2r(punpcklwd, var, reg)
00523 #define punpcklwd_r2r(regs, regd)   mmx_r2r(punpcklwd, regs, regd)
00524 #define punpcklwd(vars, vard)       mmx_m2m(punpcklwd, vars, vard)
00525 
00526 #define punpcklbw_m2r(var, reg)     mmx_m2r(punpcklbw, var, reg)
00527 #define punpcklbw_r2r(regs, regd)   mmx_r2r(punpcklbw, regs, regd)
00528 #define punpcklbw(vars, vard)       mmx_m2m(punpcklbw, vars, vard)
00529 
00530 /*
00531     2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
00532     (interleaves high half of dest with high half of source
00533     as padding in each result field)
00534 */
00535 #define punpckhdq_m2r(var, reg)     mmx_m2r(punpckhdq, var, reg)
00536 #define punpckhdq_r2r(regs, regd)   mmx_r2r(punpckhdq, regs, regd)
00537 #define punpckhdq(vars, vard)       mmx_m2m(punpckhdq, vars, vard)
00538 
00539 #define punpckhwd_m2r(var, reg)     mmx_m2r(punpckhwd, var, reg)
00540 #define punpckhwd_r2r(regs, regd)   mmx_r2r(punpckhwd, regs, regd)
00541 #define punpckhwd(vars, vard)       mmx_m2m(punpckhwd, vars, vard)
00542 
00543 #define punpckhbw_m2r(var, reg)     mmx_m2r(punpckhbw, var, reg)
00544 #define punpckhbw_r2r(regs, regd)   mmx_r2r(punpckhbw, regs, regd)
00545 #define punpckhbw(vars, vard)       mmx_m2m(punpckhbw, vars, vard)
00546 
00547 /*
00548     Empty MMx State
00549     (used to clean-up when going from mmx to float use
00550     of the registers that are shared by both; note that
00551     there is no float-to-mmx operation needed, because
00552     only the float tag word info is corruptible)
00553 */
00554 #define emms()                      __asm__ __volatile__ ("emms")
00555 
00556 #if defined(USE_SSE2)
00557 #define movdqu_m2r(var, reg)        mmx_m2r(movdqu, var, reg)
00558 #define movdqu_r2m(reg, var)        mmx_r2m(movdqu, reg, var)
00559 #define movdqu_r2r(regs, regd)      mmx_r2r(movdqu, regs, regd)
00560 
00561 #define movdqa_m2r(var, reg)        mmx_m2r(movdqa, var, reg)
00562 #define movdqa_r2m(reg, var)        mmx_r2m(movdqa, reg, var)
00563 #define movdqa_r2r(regs, regd)      mmx_r2r(movdqa, regs, regd)
00564 
00565 #define psrldq_i2r(imm, reg)        mmx_i2r(psrldq, imm, reg)
00566 #define psrldq_m2r(var, reg)        mmx_m2r(psrldq, var, reg)
00567 #define psrldq_r2r(regs, regd)      mmx_r2r(psrldq, regs, regd)
00568 #define psrldq(vars, vard)          mmx_m2m(psrldq, vars, vard)
00569 #endif
00570 
00571 #if defined(__cplusplus)
00572 }
00573 #endif
00574 
00575 #endif
00576 
00577 #endif
00578 /*- End of file ------------------------------------------------------------*/